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 RICMOSTM GATE ARRAYS
FEATURES
* Fabricated on Honeywell's Radiation Hardened 0.65 mLeff RICMOSTM IV Bulk Process * Array Sizes from 10K to 336K Available Gates (Raw) * TTL or CMOS Compatible I/O * Full Complement of Screening Flows
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HR2000
FAMILY
* Total Dose Hardness 1x106 rad(SiO2) * Dose Rate Upset Hardness 1x109 rad(Si)/sec * Dose Rate Survivability 1x1012 rad (Si)/sec * Soft Error Rate 1x10-10 Errors/Bit/Day * Neutron Fluence Hardness to 1x1014/cm2 * No Latchup
* Configurable Multi-Port Gate Array SRAM * Modular Custom Drop-In SRAM Capability * Supports 5V Operation * Supports System Speeds Beyond 75 MHz
GENERAL DESCRIPTION
The HR2000 gate arrays are performance oriented seaof-transistor arrays, fabricated on Honeywell's 0.65 m RICMOSTM IV bulk CMOS process. The high density and performance characteristics of the RICMOS (Radiation Insensitive CMOS) process make possible device operation beyond 75 MHz over the full military temperature range, even after exposure to ionizing radiation exceeding 1x106 rad(SiO2). Flip-Flops have been designed for a Soft Error Rate (SER) of less than 1x10-10 errors/bit/day in the Adams 90% worst case environment. Each HR2000 design is founded on our proven RICMOS ASIC library of SSI and MSI logic elements, configurable RAM cells and selectable I/O pads. The gate arrays feature a global clock network capable of handling multiple clock signals with low clock skew between registers. This family is fully compatible with Honeywell's high reliability screening procedures and consistent with QML Class Q and V requirements. Designers can choose from a wide variety of I/O types. Output buffer options include 5 drive strengths, CMOS/ TTL levels, IEEE 1149.1 boundary scan, pull-up/pulldown resistors, and three-state capability. Input buffers can be selected with CMOS/TTL/Schmitt trigger levels, IEEE 1149.1 boundary scan and pull-up/pull-down resistors. Bi-directional buffers are also available. The HR2000 family provides options for configurable multi-port SRAMs. Word widths can be selected in single bit increments. A variety of SRAM read and write port options are available to serve most applications. Custom drop-in macrocells can also be implemented to further increase chip density. Logic designers need not have prior experience in radiation hardening. Honeywell's VDSTM Toolkit and RICMOS IV libraries provide the necessary guidance to achieve first pass design success. The VDS Toolkit supports industry standard platforms including those offered by Mentor Graphics and Synopsys. Honeywell can perform design translations to the HR2000 arrays from other CAD platforms. Our synthesis capabilities allow customers to use familiar CAD tools and libraries to map the design to Honeywell library components. The HR2000 family of gate arrays is the right choice for your high reliability applications demanding high density and radiation performance. To learn more about Honeywell's variety of space components, call us at 612-954-2888.
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HR2000
HR2000 Characteristics Total Core Gate Count Usable Gate Count Maximum Die I/O Maximum Package I/O (1) Typical Delay--2 Input NAND
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HR2010 10K 7K 72 60
HR2065 68K 40K 176 172
HR2090 92 K 52K 220 220
HR2125 126K 67K 252 216
HR2210 207K 103K 314 256
HR2340 336K 158K 372 320
350 ps at 5.0V Driver, Receiver, Bi-Directional, Three-State CMOS, TTL, Schmitt Trigger 0.65 W/Gate/MHz, @ 5.0V 5V 10% -55 C to 125 C RICMOSTM IV 0.65 m Leff / 0.8 m Drawn
Selectable I/O
I/O Interface Levels Typical Power Dissipation Operating Voltage Operating Temperature Process Technology Minimum Geometry
(1) Design and package dependent
To learn more about Honeywell Solid State Electronics Center, visit our web site at http://www.ssec.honeywell.com
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Helping You Control Your World
900171 Rev. A 2/97
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